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is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 1 512 k x36 and 1024 k x18 1 8 mb synchronous pipelined single cycle deselect static ram novem ber 2014 features ? internal self - timed write cycle ? individual byte write control and global write ? clock controlled, registered address, data and ? control ? burst sequence control using mode input ? three chip enable option for simple depth expansion and address pipelining ? common data inputs and data outputs ? auto power - down during deselect ? single cycle deselect ? snooze mode fo r reduced - power standby ? jedec 100 - pin qfp , 165 - ball bga and 119 - ball bga packages ? power supply: lps : v dd 3.3v ( 5%), v ddq 3.3v/2.5v ( 5%) vps : v dd 2.5v ( 5%), v ddq 2.5v ( 5%) vvps : v dd 1.8v ( 5%), v ddq 1.8v ( 5%) ? jtag bound ary scan for bga packages ? commercial, industrial and automotive temperature support ? lead - free available ? for leaded option s , please contact issi fast access time description the 1 8 mb product family features high - speed, low - power synchronous static rams designed to provide burstable, high - performance memory for communication and networking applications. the is61lps/vps /vvps 512 36 b are organized as 524,288 words by 36bits . the is61lps/ vps/ vvps 1024 18 b are organized as 1,048,576 words by 18 bits. fabricated with issi's advanced cmos technology, the device integrates a 2 - bit burst counter, high - speed sram core, and high - drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive - edge - triggered single clock input . write cycles are internally self - timed and are initiated by the rising edge of the clock input. write cycles can be one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. the byte write operation is performed by using the byte write enable ( / bwe) input combined with one or more individual byte write signals ( / bwx). in addition, global write ( / gw) is available for writing all bytes at one time, regardless of the byte write controls. bursts can be initiated with either / adsp (address status processor) or / adsc (address status cache controller) input pins. subsequent burst addresses can be generated internally and controlled by the / adv (burst address advance) input pin. the mode pin is used to select the burst sequence order . linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left floating. copyright ? 201 4 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specification and it s products at any time without notice. issi assumes no liability arising out of the application or use of any information, produ cts or services described herein. customers are advised to obtain the latest version of this device specification before rely ing on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend th e use of any of its products in life support applications where the failure or malfunction of the product can reasonably be e xpected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not author ized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integra ted silicon solution, inc is adequately protected under the circumstances symbol parameter - 250 - 200 units tkq clock access time 2.6 3. 0 ns tkc cycle time 4 5 ns frequency 250 200 mhz
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 2 block diagram
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 3 pin configuration 512 k x 3 6 , 165 - ball bga (top view) 1 2 3 4 5 6 7 8 9 10 11 a nc a /ce /bwc /bwb /ce2 /bwe /adsc /adv a nc b nc a ce2 /bwd /bwa clk /gw /oe /adsp a nc c dqpc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpb d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb h nc v ss nc v dd v ss v ss v ss v dd nc nc zz j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa n dqpd nc v ddq v ss nc a v ss v ss v ddq nc dqpa p nc nc a a tdi a1* tdo a a a a r mode nc a a tms a0* tck a a a a note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. bottom view 165 - ball, 13 mm x 15mm bga pin descriptions symbol pin name clk synchronous clock a0,a1 synchronous burst address inputs a address inputs / adv synchronous burst address advance /adsp address status processor /adsc address status controller mode burst sequence selection /ce,ce2,/ce2 synchronous chip enable / bwe byte write enable /bwx (x=a - d) synchronous byte write inputs / gw global write enable /oe output enable dqx data inputs/outputs dqpx parity data i/o tck,tdi, tdo,tms jtag pins zz power sleep mode nc no connect v dd power supply v ddq i/o power supply v ss ground
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 4 1024 k x 18 , 165 - ball bga (top view) 1 2 3 4 5 6 7 8 9 10 11 a nc a /ce /bw b nc /ce2 /bwe /adsc /adv a a b nc a ce2 nc /bwa clk /gw /oe /adsp a nc c nc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqp a d nc dq b v ddq v dd v ss v ss v ss v dd v ddq nc dq a e nc dq b v ddq v dd v ss v ss v ss v dd v ddq nc dq a f nc dq b v ddq v dd v ss v ss v ss v dd v ddq nc dq a g nc dq b v ddq v dd v ss v ss v ss v dd v ddq nc dq a h nc v ss nc v dd v ss v ss v ss v dd nc nc zz j dq b nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc k dq b nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc l dq b nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc m dq b nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc n dqp b nc v ddq v ss nc a nc v ss v ddq nc nc p nc nc a a tdi a1* tdo a a a a r mode nc a a tms a0* tck a a a a note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. pin description bottom view 165 - ball, 13 mm x 15mm bga symbol pin name clk synchronous clock a0,a1 synchronous burst address inputs a address inputs / adv synchronous burst address advance /adsp address status processor /adsc address status controller mode burst sequence selection ce, /ce, ce2 synchronous chip enable / bwe byte write enable /bwx (x=a - b) synchronous byte write inputs / gw global write enable /oe output enable dqx data inputs/outputs tck,tdi, tdo,tms jtag pins zz power sleep mode nc no connect v dd power supply v ddq i/o power supply v ss ground
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 5 512k x 36, 119 - ball bga (top view) 1 2 3 4 5 6 7 a v ddq a a /adsp a a v ddq b nc a a /adsc a a nc c nc a a v dd a a nc d dqc dqpc v ss nc v ss dqpb dqb e dqc dqc v ss /ce v ss dqb dqb f v ddq dqc v ss /oe v ss dqb v ddq g dqc dqc /bwc /adv /bwb dqb dqb h dqc dqc v ss /gw v ss dqb dqb j v ddq v dd nc v dd nc vdd v ddq k dqd dqd v ss clk v ss dqa dqa l dqd dqd /bwd nc /bwa dqa dqa m v ddq dqd v ss /bwe v ss dqa v ddq n dqd dqd v ss a1* v ss dqa dqa p dqd dqpd v ss a0* v ss dqpa dqa r nc a mode vdd nc a nc t nc nc a a a nc zz u v ddq tms tdi tck tdo nc v ddq note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. bottom view 119 - ball, 14 mm x 22 mm bga pin descriptions symbol pin name clk synchronous clock a0,a1 synchronous burst address inputs a address inputs / adv synchronous burst address advance /adsp address status processor /adsc address status controller mode burst sequence selection /ce synchronous chip enable / bwe byte write enable /bwx (x=a - d) synchronous byte write inputs / gw global write enable /oe output enable dqx data inputs/outputs tck,tdi, tdo,tms jtag pins zz power sleep mode nc no connect v dd power supply v ddq i/o power supply v ss ground
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 6 1024 k x 18 , 1 19 - ball bga (top view) 1 2 3 4 5 6 7 a v ddq a a /adsp a a v ddq b nc a a /adsc a a nc c nc a a v dd a a nc d dqb nc v ss nc v ss dqpa nc e nc dqb v ss / ce v ss nc dqa f v ddq nc v ss / oe v ss dqa v ddq g nc dqb / bwb /adv v ss nc dqa h dqb nc vss / gw v ss dqa nc j v ddq v dd nc v dd nc v dd v ddq k nc dqb vss clk v ss nc dqa l dqb nc v ss nc / bwa dqa nc m v ddq dqb v ss / bwe v ss nc v ddq n dqb nc v ss a1* v ss dqa nc p nc dqpb v ss a0* v ss nc dqa r nc a mode v dd nc a nc t nc a a nc a a zz u v ddq tms tdi tck tdo nc v ddq note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. pin descriptions bottom view 119 - ball, 14 mm x 22 mm bga symbol pin name clk synchronous clock a0,a1 synchronous burst address inputs a address inputs / adv synchronous burst address advance /adsp address status processor /adsc address status controller mode burst sequence selection /ce synchronous chip enable / bwe byte write enable /bwx (x=a - b ) synchronous byte write inputs / gw global write enable /oe output enable dqx data inputs/outputs dqpx parity data i/o tck,tdi, tdo,tms jtag pins zz power sleep mode nc no connect v dd power supply v ddq i/o power supply v ss ground
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 7 512 k x 36 , 100pin qfp (top view) note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. pin descriptions symbol pin name symbol pin name clk synchronous clock / gw global write enable a0,a1 synchronous burst address inputs /oe output enable a address inputs dqx data inputs/outputs / adv synchronous burst address advance dqpx parity data i/o /adsp address status processor zz power sleep mode /adsc address status controller nc no connect mode burst sequence selection v dd power supply /ce,ce2,/ce2 synchronous chip enable v ddq i/o power supply / bwe byte write enable v ss ground /bwx (x=a - d ) synchronous byte write inputs a a /ce ce2 /bwd /bwc /bwb /bwa /ce2 vdd vss clk /gw /bwe /oe /adsc /adsp /adv a a 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 dqpc 1 80 dqpb dqc 2 79 dqb dqc 3 78 dqb vddq 4 77 vddq vss 5 76 vss dqc 6 75 dqb dqc 7 74 dqb dqc 8 73 dqb dqc 9 72 dqb vss 10 71 vss vddq 11 70 vddq dqc 12 69 dqb dqc 13 68 dqb nc 14 67 vss vdd 15 66 nc nc 16 65 vdd vss 17 64 zz dqd 18 63 dqa dqd 19 62 dqa vddq 20 61 vddq vss 21 60 vss dqd 22 59 dqa dqd 23 58 dqa dqd 24 57 dqa dqd 25 56 dqa vss 26 55 vss vddq 27 54 vddq dqd 28 53 dqa dqd 29 52 dqa dqpd 30 51 dqpa 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 mode a a a a a1 a0 nc nc vss vdd a a a a a a a a a 512k x 36
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 8 1024 k x 18 , 100pin qfp (top view) note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. pin descriptions symbol pin name symbol pin name clk synchronous clock / gw global write enable a0,a1 synchronous burst address inputs /oe output enable a address inputs dqx data inputs/outputs / adv synchronous burst address advance zz power sleep mode /adsp address status processor nc no connect /adsc address status controller v dd power supply mode burst sequence selection v ddq i/o power supply /ce,ce2,/ce2 synchronous chip enable v ss ground / bwe byte write enable /bwx (x=a - b) synchronous byte write inputs a a /ce ce2 nc nc /bwb /bwa /ce2 vdd vss clk /gw /bwe /oe /adsc /adsp /adv a a 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 nc 1 80 a nc 2 79 nc nc 3 78 nc vddq 4 77 vddq vss 5 76 vss nc 6 75 nc nc 7 74 dqpa dqb 8 73 dqa dqb 9 72 dqa vss 10 71 vss vddq 11 70 vddq dqb 12 69 dqa dqb 13 68 dqa nc 14 67 vss vdd 15 66 nc nc 16 65 vdd vss 17 64 zz dqb 18 63 dqa dqb 19 62 dqa vddq 20 61 vddq vss 21 60 vss dqb 22 59 dqa dqb 23 58 dqa dqpb 24 57 nc nc 25 56 nc vss 26 55 vss vddq 27 54 vddq nc 28 53 nc nc 29 52 nc nc 30 51 nc 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 mode a a a a a1 a0 nc nc vss vdd a a a a a a a a a 1024k x 18
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 9 truth table synchronous truth table operation address /ce /ce2 ce2 zz /adsp /adsc /adv /write /oe clk dq deselect cycle, power - down none h x x l x l x x x l - h high - z desel ect cycle, power - down none l x l l l x x x x l - h high - z desel ect cycle, power - down none l h x l l x x x x l - h high - z desel ect cycle, power - down none l x l l h l x x x l - h high - z deselect cycle, power - down none l h x l h l x x x l - h high - z snooz e mode, power - down none x x x h x x x x x x high - z read cycle, begin burst external l l h l l x x x l l - h q read cycle, begin burst external l l h l l x x x h l - h high - z write cycle, begin burst external l l h l h l x l x l - h d read cycle, begin burst external l l h l h l x h l l - h q read cycle, begin burst external l l h l h l x h h l - h high - z read cycle, continue burst next x x x l h h l h l l - h q read cycle, continue burst next x x x l h h l h h l - h high - z read cycle, continue burst next h x x l x h l h l l - h q read cycle, continue burst next h x x l x h l h h l - h high - z write cycle, continue burst next x x x l h h l l x l - h d write cycle, continue burst next h x x l x h l l x l - h d read cycle, suspend burst current x x x l h h h h l l - h q read cycle, suspend burst current x x x l h h h h h l - h high - z read cycle, suspend burst current h x x l x h h h l l - h q read cycle, suspend burst current h x x l x h h h h l - h high - z write cycle, suspend burst current x x x l h h h l x l - h d write cycle, suspend burst current h x x l x h h l x l - h d note: 1. x means dont care. h means logic high. l means logic low. 2. for write, l means one or more byte write enable signals ( / bwa - d) and / bwe are low or / gw is low. / write = h for all / bwx, / bwe, / gw high. 3. / bwa enables writes to dqas and dqpa. / bwb enables wri tes to dqbs and dqpb. / bwc enables writes to dqcs and dqpc. / bwd enables writes to dqds and dqpd. dqpa and dqpb are available on the x18 version. dqpa - dqpd are available on the x36 version. 4. all inputs except / oe and zz must meet setup and hold times aro und the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, / oe must be high before the input data setup time and held high during the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high - z during power - up. 8. / adsp low always initiates an internal read at the l - h edge of clk. a write is performed by setting one or more byte write enable signals and / bwe low or / gw low for the subsequent l - h edge of clk. see write timing diagram for clarification.
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 10 partial truth table operation / gw / b we /bwa /bwb /bwc /bwd read h h x x x x read h l h h h h write byte a h l l h h h write byte b h l h l h h write byte c h l h h l h write byte d h l h h h l write all bytes h l l l l l write all bytes l x x x x x notes: 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk. address sequence in burst mode interleaved burst address table (mode = v dd or nc) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = v ss ) power up sequence v ddq v dd 1 i/o pins 2 notes: 1. v dd can be applied at the same time as v ddq 2. applying i/o inputs is recommended after v ddq is stable. the inputs of the i/o pins can be applied at the same time as v ddq as long as vih (level of i/o pins) is lower than v ddq . absolute maximum ratings and operating range a1', a0' = 1,1 0,0 1,0 0,1
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 11 absolute maximum ratings symbol parameter lps value vps / vvps value unit tstg storage temperature C 65 to +150 C 65 to +150 c pd power dissipation 1.6 1.6 w iout output current (per i/o) 20 20 ma vin, vout voltage relative to vss for i/o pins C 0.5 to v ddq +0.3 C 0.5 to v ddq + 0.3 v vin voltage relative to vss for address and control inputs C 0.3 to v dd +0.5 C 0.3 to v dd + 0.3 v notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specif ication is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high - impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high - z at power up. operating range (is61 lps x) range ambient tempera ture v dd v ddq commercial 0c to +70c 3.3v 5% 3.3v / 2.5v 5% industrial - 40c to +85c 3.3v 5% 3.3v / 2.5v 5% automotive - 40c to +125c 3.3v 5% 3.3v / 2.5v 5% operating range (is61 vps x) range ambient temperature v dd v ddq commercial 0c to +70c 2.5v 5% 2.5v 5% industrial - 40c to +85c 2.5v 5% 2.5v 5% automotive *please contact issi operating range (is61 vvps x) range ambient temperature v dd v ddq commercial 0c to +70c 1.8v 5% 1.8v 5% industrial - 40c to +85c 1.8v 5% 1.8v 5% automotive *please contact issi
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 12 characteristics dc electrical characteristics (over operating temperature r ange) symbo l parameter test conditions 3.3v 2.5v 1.8v unit min. max. min. max. min. max. voh output high voltage ioh= - 4.0 ma(3.3v) 2.4 2.0 v ddq - 0.4 v ioh= C 1.0 ma(2.5v,1.8v) vol output low voltage iol=8.0 ma(3.3v) 0.4 0.4 0.4 v iol=1. 0 ma(2.5v,1.8v) vih input high voltage 2.0 v dd +0.3 1.7 v dd +0.3 0.7 * v dd v dd +0.3 v vil input low voltage C 0.3 0.8 C 0.3 0.7 C 0.3 0.3* v dd v ili input leakage current vssvin v dd C 1 1 C 1 1 C 1 1 a ilo output leakage current vssvout v ddq ,/oe=vih C 1 1 C 1 1 C 1 1 a notes: 1. all voltages referenced to ground. 2. overshoot: 3.3v and 2.5v: vih (ac) v dd + 1.5v (pulse width less than tkc /2) 1.8v: vih (ac) v dd + 0.5v (pulse width less than tkc /2) 3. undershoot: 3.3v and 2.5v: vil (ac) - 1.5v (pulse width less than tkc /2) 1.8v: vil (ac) - 0.5v (pulse width less than tkc /2) 4. mode pin has an internal pull - up and should be tied to v dd or vss . it exhibits 100a maximum leakage current when tied to vss+0.2v or v dd C 0.2v. 5. zz pin has an internal pull - down and should be tied t o v dd or vss . it exhibits 100a maximum leakage current when tied to vss+0.2v or v dd C 0.2v. power supply characteristics (over operating range) symbol parameter test conditions temp. range - 250 - 200 unit max max x18 x36 x18 x36 icc ac operating, supply current device selected, oe = vih, zz vil,all inputs 0.2v or v dd C 0.2v,cycle time tkc min. com. 270 270 220 220 ma ind. 290 290 240 240 isb standby current ttl input device deselected, v dd = max.,all inputs vil or vih,zz vil, f = max. com. 80 80 70 70 ma ind. 90 90 80 80 isb1 standby current cmos input device deselected, v dd = max.,vin vss + 0.2v or v dd C 0.2v,f = 0 com. 60 60 60 60 ma ind. 70 70 70 70 note: 1. power - up assumes a linear ramp from 0v to v dd (min) within 200ms. during this time vih < v dd and v ddq < v dd
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 13 capacitance symbol parameter conditions max. unit cin input capacitance vin = 0v 6 pf cout input/output capacitance vout = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: ta = 25c, f = 1 mhz, v dd = 3.3v. read/write cycle switching characteristics (over operating range) symbol parameter - 250 - 200 unit min. max. min. max. f max clock frequency 250 200 mhz t kc cycle time 4 5 ns t kh clock high time 1.7 2 ns t kl clock low time 1.7 2 ns t kq clock access time 2.6 3. 0 ns t kqx (2) clock high to output invalid 0.8 1.5 ns t kqlz (2,3) clock high to output low - z 0.8 1 ns t kqhz (2,3) clock high to output high - z 2.6 3. 0 ns t oeq output enable to output valid 2.6 3. 0 ns t oelz (2,3) output enable to output low - z 0 0 ns t oehz (2,3) output disable to output high - z 2.6 3 .0 ns t as address setup time 1. 2 1.4 ns t ws read/write setup time 1. 2 1.4 ns t ces chip enable setup time 1. 2 1.4 ns t se clock enable setup time 1. 2 1.4 ns t advs address advance setup time 1. 2 1.4 ns t ds data setup time 1. 2 1.4 ns t ah address hold time 0. 3 0.4 ns t he clock enable hold time 0. 3 0.4 ns t wh write hold time 0. 3 0.4 ns t ceh chip enable hold time 0. 3 0.4 ns t advh address advance hold time 0.3 0.4 ns t dh data hold time 0.3 0.4 ns notes: 1. configuration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 14 3.3v i/o ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing and reference level 1.5v v tt 1.5v v load 3.3v r1, r2 317, 351 output load see figures 1 and 2 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing and reference level 1.25v v tt 1.25v v load 2.5v r1, r2 1667, 1538 output load see figures 1 and 2 1.8v i/o ac test conditions parameter unit input pulse level 0v to 1.8v input rise and fall times 1.5 ns input and output timing and reference level 0.9v v tt 0.9v v load 1.8v r1, r2 1k, 1k output load see figures 1 and 2 i/o output load equivalent 50 ? output z o =50 ? v tt v load output 5 pf including jig and scope r2 r1 figure1 figure 2
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 15 read cycle timing dataout address datain / adsc / adsp / adv clk / bwe ce2 / ce2 / bwx / gw / oe / ce tces high - z high - z tss tas rd1 single read tws tceh tkh toeq tkq tkc 1a toeqx tkl tavs tavh ce2 and / ce2 only sampled with / adsp or / adsc toehz 2a 2b burst read / adsp is blocked by / ce inactive / ce masks / adsp / adsc initiate read 2c 2d pipelined read rd3 unselected with ce2 tkqhz tkqx unselected rd 2 tkq lz t oelz suspend burst t s h tss t s h t a h t w h tws t w h tceh tces tceh tces
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 16 write cycle timing high - z dataout address datain / adsc / adsp / adv clk / bwe / ce2 ce2 / bwx / oe / gw / ce high - z tss tas single write tds tdh / adv must be inactive for / adsp write tws tkh tkc tkl ce2 and / ce2 only sampled with / adsp or / adsc / ce masks / adsp burst write tavs / adsp is blocked by / ce inactive / adsc initiate s write write wr3 wr3 unselected unselected with ce2 t s h t av h wr 2 wr 1 t a h t w h t w h tws wr 2 wr 1 tws t w h t w h tws t ces t ceh t ceh t ces t ceh t ces / bw 1 - / bw 4 only are applied to first cycle of wr2 1a 2a 2b 2c 2d 3a
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 17 snooze mode electrical characteristics symbol parameter conditions temperature range min. max. unit isb2 current during snooze mode zz vih com. 30 ma ind. 35 auto. 40 tpds zz active to input ignored 2 cycle tpus zz inactive to input sampled 2 cycle tzzi zz active to snooze current 2 cycle trzzi zz inactive to exit snooze current 0 ns sleep mode timing clk zz isupply all inputs (except zz) tpds tzzi isb2 trzzi deselect or read only deselect or read only zz setup cycle normal operation cycle outputs (q) don't care high - z zz recovery cycle tp u s
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 18 ieee 1149.1 tap and boundary scan the sram provides a limited set of jtag functions to test the interconnection between sram i/os and printed circuit board traces or other components. there is no multiplexer in the path from i/o pins to the ram core. in conformance with ieee standard 1149.1, the sram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. the tap controller has a standard 16 - state machine that resets internally on power - up. therefore , a trst signal is not required disabling the jtag feature the sram can operate without using the jtag feature. to disable the tap controller, tck must be tied low (vss) to prevent clocking of the device. tdi and tms are internally pulled up and may be lef t disconnected. they may alternately be connected to v dd through a pull - up resistor. tdo should be left disconnected. on power - up, the device will come up in a reset state, which will not interfere with device operation. test access port signal list: 1. te st clock (tck) this signal uses v dd as a power supply. the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. 2. test mode select (tms) this signal uses v dd as a power supply. the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. 3. test data - in (tdi) this signal uses v dd as a power supply. the tdi input is used to serially input test instructions and infor mation into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. tdi is connected to the most significant bit (msb) of any r egister. for more information regarding instruction register loading, please see the tap controller state diagram. 4. test data - out (tdo) this signal uses v dd as a power supply. the tdo output ball is used to serially clock test instructions and data out from the registers. the tdo output driver is only active during the shift - ir and shift - dr tap controller states. in all other states, the tdo pin is in a high - z state. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. for more information, please see the tap controller state diagram.
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 19 tap controller state and block diagram tap controller state machine 90 b y p a s s r e g i s t e r ( 1 b i t ) i d e n t i f i c a t i o n r e g i s t e r ( 3 2 b i t s ) i n s t r u c t i o n r e g i s t e r ( 3 b i t s ) t a p c o n t r o l l e r t d o t m s t c k t d i c o n t r o l s i g n a l s b o u n d a r y s c a n r e g i s t e r ( 7 5 b i t s ) . . . t e s t l o g i c r e s e t s e l e c t d r r u n t e s t i d l e 0 1 1 c a p t u r e d r 0 1 0 0 1 0 1 1 0 s h i f t d r e x i t 1 d r p a u s e d r e x i t 2 d r 1 1 u p d a t e d r 0 s e l e c t i r 1 c a p t u r e i r 0 1 0 0 1 0 1 s h i f t i r e x i t 1 i r p a u s e i r e x i t 2 i r 1 1 u p d a t e i r 0 0 0 1 0 1 0
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 20 performing a tap reset a reset is performed by forcing tms high ( v dd ) for five rising edges of tck. reset may be performed while the sram is operating and does not affect its operation. at power - up, the tap is internally reset to ensure that tdo comes up in a high - z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through th e instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. 1. instruction register this register is loaded during the update - ir state of the tap controller. at power - up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture - ir state, t he two lsbs are loaded with a binary 01 pattern to allow for fault isolation of the board - level serial test data path. 2. bypass register the bypass register is a single - bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. 3. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. several b alls are also included in the scan register to reserved balls. the boundary scan register is loaded with the contents of the sram input and output ring when the tap controller is in the capture - dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift - dr state. each bit corresponds to one of the balls on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. 4. identification (id) register the id register is loaded with a ve ndor - specific, 32 - bit code during the capture - dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift - dr state. scan register sizes registe r name bit size instruction 3 bypass 1 id 32 boundary scan 90 tap instruction set many instructions are possible with an eight - bit instruction register and all valid combinations are listed in the tap instruction code table. all other instruction codes that are not listed on this table are reserved and should not be used. instructions are loaded into the tap controller during the shift - ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted from the instruction register through the tdi and tdo pins. to execute an instruction once it is shifted in, the tap controller must be moved into the update - ir state.
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 21 1. extest the extest instruction allows circuitry external to the component package to be tested. boundary - scan register cells at output balls are used to apply a test vector, while those at input balls capture test results. typically, the first test vector to be applied using the extest instruction will be shifted into the boundary scan reg ister using the preload instruction. thus, during the update - ir state of extest, the output driver is turned on, and the preload data is driven onto the output balls. 2. idcode the idcode instruction causes a vendor - specific, 32 - bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift - dr state. the idcode instruction is loaded into the instruction register upon power - up or whenever the tap controller is given a test logic reset state. 3. sample z if the sample - z instruction is loaded in the instruction register, all sram outputs are forced to an inactive drive state (high - z), moving the tap control ler into the capture - dr state loads the data in the srams input into the boundary scan register, and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift - dr state. 4. sample/preload when the sample/prel oad instruction is loaded into the instruction register and the tap controller is in the capture - dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that the tap controller cl ock can only operate at a frequency up to 1 0 mhz, while the sram clock operates significantly faster. because there is a large difference between the clock frequencies, it is possible that during the capture - dr state, an input or output will undergo a tran sition. the tap may then try to capture a signal while in transition. this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to ensure that the boundary scan register will cap ture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controllers capture setup plus hold time. the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock du ring a sample/ preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by put ting the tap into the shift - dr state. this places the boundary scan register between the tdi and tdo balls. 6. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift - dr state, the bypass register is place d between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. 7. reserved these instructions are not implemented but are reserved for future use. please do not use these instructions.
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 22 jtag dc operating characteristics (over the operating temperature range , 2.5v and 3.3v option) parameter symbol min max units notes jtag input high voltage v ih1 2.0 v dd +0.3 v jtag input low voltage v il1 C oh1 1.7 - v |i oh1 | = 2ma jtag output low voltage v ol1 - 0.7 v i ol1 = 2m a jtag output high voltage v oh2 2.1 - v |i oh2 | = 100a jtag output low voltage v ol2 - 0.2 v i ol2 = 100 a jtag input leakage current i lijtag - 10 +10 a 0 vin v dd jtag output leakage current i lojtag - 10 +10 a 0 vout v dd notes: 1. all voltages referenced to vss (gnd) ; all jtag inputs and outputs are lvttl - compatible . jtag dc operating characteristics (over the operating temperature range , 1.8v option) parameter symbol min max units notes jtag input high voltage v ih1 tbd tbd v jtag input low voltage v il1 tbd tbd v jtag output high voltage v oh1 tbd tbd v jtag output low voltage v ol1 tbd tbd v jtag input leakage current i lijtag tbd tbd a jtag output leakage current i lojtag tbd tbd a notes: 1. all voltages referenced to vss (gnd) ; all jtag inputs and outputs are lvttl - compatible . jtag ac test conditions (over the operating temperature range) parameter symbol 1.8v option 2.5v option 3.3v option units input pulse high level v ih1 tbd 2.5 3.0 v input pulse low level v il1 tbd 0 0 v input r ise and fall t ime t r1 tbd 1.5 1.5 ns test load termination supply voltage v ref tbd 1.25 1.5 v input and output timing reference level v ref tbd 1.25 1.5 v tap output load equivalent v r e f t e s t c o m p a r a t o r o u t p u t 5 0 2 0 p f 5 0 v r e f
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 23 jtag ac characteristics (over the operating temperature range) parameter symbol min max units tck cycle time t thth 10 0 C thtl 4 0 C tlth 4 0 C mvth 10 C thmx 10 C dvth 10 C thdx 10 C tlov C jtag timing diagram t c k t m s t t h t h t t h t l t t l t h t t h m x t m v t h t d i t d o t t l o v t t h d x t d v t h
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 24 instruction set code instruction tdo output notes 000 extest boundary scan register 2, 6 001 idcode 32 - bit identification register 010 sample - z boundary scan register 1, 2 011 reserved do not use 5 100 sample (/preload) boundary scan register 4 101 reserved do not use 5 110 reserved do not use 5 111 bypass bypass register 3 notes: 1. places d qs in high - z in order to sample all input data, regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds the last serially loaded tdi when exiting the shift - dr state. 4. sample instruction does not place d qs in high - z. 5. this instruction is reserved. invoking this instruction will cause imprope r sram functionality. 6. by default, it places d q s in high - z. if the internal register on the scan chain is set high, d q s will be updated with information loaded via a previous sample instruction. the actual transfer occurs during the update ir state after ex test is loaded. the value of the internal register can be changed during sample and extest only. id register definition instruction field description 512 k x 36 1024 k x 18 revision number (31:28) reserved for version number. xxxx xxxx device depth (27:23) defines depth of sram. 512 k or 1024 k 00111 0 100 0 device width (22:18) defines width of the sram. x36 or x18 00100 00011 issi device id (17:12) reserved for future use. xxxxx x xxxxx x issi jedec id (11:1) allows unique identification of sram vendor. 0000 1010101 0000 1010101 id register presence (0) indicate the presence of an id register. 1 1
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 25 165 bga boundary scan order 165 bga x36 x18 bit # bump id signal bump id signal 1 n6 a9 n6 a9 2 n7 nc n7 nc 3 n10 nc n10 nc 4 p11 a8 p11 a8 5 p8 a18 p8 a18 6 r8 a17 r8 a17 7 r9 a16 r9 a16 8 p9 a15 p9 a15 9 p10 a14 p10 a14 10 r10 a13 r10 a13 11 r11 a12 r11 a12 12 h11 zz h11 zz 13 n11 dqa0 n11 nc 14 m11 dqa1 m11 nc 15 l11 dqa2 l11 nc 16 m10 dqa3 m10 dqa8 17 l10 dqa4 l10 dqa7 18 k11 dqa5 k11 nc 19 j11 dqa6 j11 nc 20 k10 dqa7 k10 dqa6 21 j10 dqa8 j10 dqa5 22 h9 nc h9 nc 23 h10 nc h10 nc 24 g11 dqb8 g11 dqa4 25 f11 dqb7 f11 dqa3 26 g10 dqb6 g10 nc 27 e11 dqb5 e11 dqa2 28 d11 dqb4 d11 dqa1 29 f10 dqb3 c11 dqa0 30 e10 dqb2 e10 nc 31 d10 dqb1 d10 nc 32 c11 dqb0 f10 nc 33 a11 nc a11 a19 34 b11 nc b11 nc 35 a10 a11 a10 a11 36 b10 a10 b10 a10 37 a9 /adv a9 /adv 38 b9 /adsp b9 /adsp 39 c10 nc c10 nc 40 a8 /adsc a8 /adsc continued on next page
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 26 165 bga x36 x18 bit # bump id signal bump id signal 41 b8 /oe b8 /oe 42 a7 /bwe a7 /bwe 43 b7 /gw b7 /gw 44 b6 clk b6 clk 45 a6 /ce2 a6 /ce2 46 b5 /bwa b5 /bwa 47 a5 /bwb a5 nc 48 a4 /bwc a4 /bwb 49 b4 /bwd b4 nc 50 b3 ce2 b3 ce2 51 a3 /ce1 a3 /ce1 52 a2 a7 a2 a7 53 b2 a6 b2 a6 54 c2 nc c2 nc 55 b1 nc b1 nc 56 a1 nc a1 nc 57 c1 dqc0 c1 nc 58 d1 dqc1 d1 nc 59 e1 dqc2 e1 nc 60 d2 dqc3 d2 dqb8 61 e2 dqc4 e2 dqb7 62 f1 dqc5 f1 nc 63 g1 dqc6 g1 nc 64 f2 dqc7 f2 dqb6 65 g2 dqc8 g2 dqb5 66 h1 nc h1 nc 67 h2 nc h2 nc 68 h3 nc h3 nc 69 j1 dqd8 j1 dqb4 70 k1 dqd7 k1 dqb3 71 j2 dqd6 j2 nc 72 l1 dqd5 l1 dqb2 73 m1 dqd4 m1 dqb1 74 k2 dqd3 n1 dqb0 75 l2 dqd2 l2 nc 76 m2 dqd1 m2 nc 77 n1 dqd0 k2 nc 78 n2 nc n2 nc 79 p1 nc p1 nc 80 r1 mode r1 mode continued on next page
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 2 7 165 bga x36 x18 bit # bump id signal bump id signal 81 r2 nc r2 nc 82 p3 a5 p3 a5 83 r3 a4 r3 a4 84 p2 nc p2 nc 85 p4 a2 p4 a2 86 r4 a3 r4 a3 87 n5 nc n5 nc 88 p6 a1 p6 a1 89 r6 a0 r6 a0 90 * int * int
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 28 119 bga boundary scan order tbd
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 29 ordering information commercial range: 0c to +70 c v dd speed x36 x18 package v dd =3.3v, v ddq =2.5v/3.3v 250mhz is61lp s 51236b - 250tq is61lp s 102418b - 250tq 100 qfp is61lp s 51236b - 250b3 is61lp s 102418b - 250b3 165 bga is61lp s 51236b - 250b2 is61lp s 102418b - 250b2 119 bga is61lp s 51236b - 250tql is61lp s 102418b - 250tql 100 qfp, lead - free is61lp s 51236b - 250b3l is61lp s 102418b - 250b3l 165 bga, lead - free is61lp s 51236b - 250b2l is61lp s 102418b - 250b2l 119 bga, lead - free 200mhz is61lp s 51236b - 200tq is61lp s 102418b - 200tq 100 qfp is61lp s 51236b - 200b3 is61lp s 102418b - 200b3 165 bga is61lp s 51236b - 200b2 is61lp s 102418b - 200b2 119 bga is61lp s 51236b - 200tql is61lp s 102418b - 200tql 100 qfp, lead - free is61lp s 51236b - 200b3l is61lp s 102418b - 200b3l 165 bga, lead - free is61lp s 51236b - 200b2l is61lp s 102418b - 200b2l 119 bga, lead - free v dd =2.5v, v ddq =2.5v 250mhz is61vp s 51236b - 250tq is61vp s 102418b - 250tq 100 qfp is61vp s 51236b - 250b3 is61vp s 102418b - 250b3 165 bga is61vp s 51236b - 250b2 is61vp s 102418b - 250b2 119 bga is61vp s 51236b - 250tql is61lp s 102418b - 250tql 100 qfp, lead - free is61vp s 51236b - 250b3l is61vp s 102418b - 250b3l 165 bga, lead - free is61vp s 51236b - 250b2l is61vp s 102418b - 250b2l 119 bga, lead - free 200mhz is61vp s 51236b - 200tq is61vp s 102418b - 200tq 100 qfp is61vp s 51236b - 200b3 is61vp s 102418b - 200b3 165 bga is61vp s 51236b - 200b2 is61vp s 102418b - 200b2 119 bga is61vp s 51236b - 200tql is61vp s 102418b - 200tql 100 qfp, lead - free is61vp s 51236b - 200b3l is61vp s 102418b - 200b3l 165 bga, lead - free is61vp s 51236b - 200b2l is61vp s 102418b - 200b2l 119 bga, lead - free v dd =1.8v, v ddq =1.8v 250mhz *please contact issi marketing 200mhz *please contact issi marketing
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 30 industrial range: - 40c to +85c v dd speed x36 x18 package v dd =3.3v, v ddq =2.5v/3.3v 250mhz is61lp s 51236b - 250tq i is61lp s 102418b - 250tq i 100 qfp is61lp s 51236b - 250b3 i is61lp s 102418b - 250b3 i 165 bga is61lp s 51236b - 250b2 i is61lp s 102418b - 250b2 i 119 bga is61lp s 51236b - 250tql i is61lp s 102418b - 250tql i 100 qfp, lead - free is61lp s 51236b - 250b3l i is61lp s 102418b - 250b3l i 165 bga, lead - free is61lp s 51236b - 250b2l i is61lp s 102418b - 250b2l i 119 bga, lead - free 200mhz is61lp s 51236b - 200tq i is61lp s 102418b - 200tq i 100 qfp is61lp s 51236b - 200b3 i is61lp s 102418b - 200b3 i 165 bga is61lp s 51236b - 200b2 i is61lp s 102418b - 200b2 i 119 bga is61lp s 51236b - 200tql i is61lp s 102418b - 200tql i 100 qfp, lead - free is61lp s 51236b - 200b3l i is61lp s 102418b - 200b3l i 165 bga, lead - free is61lp s 51236b - 200b2l i is61lp s 102418b - 200b2l i 119 bga, lead - free v dd =2.5v, v ddq =2.5v 250mhz is61vp s 51236b - 250tq i is61vp s 102418b - 250tq i 100 qfp is61vp s 51236b - 250b3 i is61vp s 102418b - 250b3 i 165 bga is61vp s 51236b - 250b2 i is61vp s 102418b - 250b2 i 119 bga is61vp s 51236b - 250tql i is61lp s 102418b - 250tql i 100 qfp, lead - free is61vp s 51236b - 250b3l i is61vp s 102418b - 250b3l i 165 bga, lead - free is61vp s 51236b - 250b2l i is61vp s 102418b - 250b2l i 119 bga, lead - free 200mhz is61vp s 51236b - 200tq i is61vp s 102418b - 200tq i 100 qfp is61vp s 51236b - 200b3 i is61vp s 102418b - 200b3 i 165 bga is61vp s 51236b - 200b2 i is61vp s 102418b - 200b2 i 119 bga is61vp s 51236b - 200tql i is61vp s 102418b - 200tql i 100 qfp, lead - free is61vp s 51236b - 200b3l i is61vp s 102418b - 200b3l i 165 bga, lead - free is61vp s 51236b - 200b2l i is61vp s 102418b - 200b2l i 119 bga, lead - free v dd =1.8v, v ddq =1.8v 250mhz *please contact issi marketing 200mhz *please contact issi marketing automotive range: - 40c to +125c v dd speed x36 x18 package v dd =3.3v, v ddq =2.5v/3.3v 250mhz is64lp s 51236b - 250tqla3 is64vp s 102436b - 250tqla3 100 qfp, lead - free is64lp s 51236b - 250b3la3 is64vp s 102436b - 250b3la3 165 bga, lead - free is64lp s 51236b - 250b2la3 is64vp s 102436b - 250b2la3 119 bga, lead - free 200mhz is64lp s 51236b - 200tqla3 is64vp s 102436b - 200tqla3 100 qfp, lead - free is64lp s 51236b - 200b3la3 is64vp s 102436b - 200b3la3 165 bga, lead - free is64lp s 51236b - 200b2la3 is64vp s 102436b - 200b2la3 119 bga, lead - free v dd =2.5v, v ddq =2.5v 250mhz is64vp s 51236b - 250tqla3 is64vp s 102436b - 250tqla3 100 qfp, lead - free is64vp s 51236b - 250b3la3 is64vp s 102436b - 250b3la3 165 bga, lead - free is64vp s 51236b - 250b2la3 is64vp s 102436b - 250b2la3 119 bga, lead - free 200mhz is64vp s 51236b - 200tqla3 is64vp s 102436b - 200tqla3 100 qfp, lead - free is64vp s 51236b - 200b3la3 is64vp s 102436b - 200b3la3 165 bga, lead - free is64vp s 51236b - 200b2la3 is64vp s 102436b - 200b2la3 119 bga, lead - free *for all other voltages and options in automotive grade, please contact issi.
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 31
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 32
is61 lps 51236b/is61 vps 51236b/ is61vvps 51236b is61 lps 102418b/is61 vps 102418b/ is61vvps 102418 b integrated silicon solution, inc. - www.issi.com rev. b 10/16/201 4 33

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